The present invention relates to integrated circuits, and, more particularly, to an integrated circuit with memory and comprising an internal high voltage generation circuit for the programming and/or erasure of cells of the memory.
The development of technology is leading to the reduction of the logic supply voltage applied to internal circuits so as to achieve a constantly greater reduction in energy consumption. It is thus possible in the market today, to find logic circuits supplied with 3 volts. It is being attempted to bring this value down to 1 volt. However, this low level of logic supply is not without consequences for the performance characteristics of certain circuits.
In particular, certain memory integrated circuits such as, in particular, EEPROM type memory integrated circuits have an internal programming high voltage generation circuit. This programming high voltage generation circuit is particularly sensitive to the level of the logic supply voltage that it receives at its input. On the one hand, the level of the logic supply voltage affects the programming high voltage generated at its output. With a lower logic supply voltage, the level of the programming high voltage generated is lower. This is a source of difficulty for the programming or erasure of the memory cell.
Indeed, with a lower level of this programming high voltage (for example Vpp=9 volts with a logic supply Vcc=two volts as compared to Vpp=15 to 17 volts with a logic supply of Vcc=five volts), the quantity of charge that it will be possible to transfer from or beneath the gate is also smaller. The programmed memory cell then has greater sensitivity to the loss of charge (leakage, duration of retention of affected data). The memory cell also gives a lower reading current. Read access is therefore slower.
Furthermore, the time for which the high voltage Vpp is applied to the cells to be programmed will have to be greater. This substantially increases the time needed for the testing of the integrated circuit, as well as the time needed to initialize the integrated circuit (when it is being configured for the user with the programming of data elements in the memory).
Finally, applying a lower logic supply voltage Vcc at the input means that the oscillation frequency of the programming high voltage generator will also be lower. We are then left, at the output of the circuit for the generation of a programming high voltage Vpp, with a higher output impedance (a lower fan-out). It is then no longer possible to apply this programming high voltage Vpp to all the cells of the memory array, a quarter array or even a page at the same time. There would be a charge (a capacitive charge) at the output that would be far too high with respect to this fan-out, which would slow down the build-up of the high voltage. It is therefore not possible to consider accessing the entire memory array in the write mode or the erasure mode or even in page mode or in quarter array write mode. All that can be envisaged is to access it in xe2x80x9cbytexe2x80x9d mode, namely word by word.
It will be understood that the programming time and/or erasure time is then significantly increased, directly affecting the testing time, and, hence, the final cost of the integrated circuit. Furthermore, it does not provide for greater flexibility of access to the users of the integrated circuit, since only the xe2x80x9cbytexe2x80x9d access mode is possible, the xe2x80x9ctotalxe2x80x9d access modes having to be prohibited.
In view of the foregoing background it is therefore an object of the invention to overcome the technical problems set forth above.
In the invention, a second logic supply pad is provided on the integrated circuit enabling the direct supply, by another external logic supply source, of the internal high voltage generation circuit. This circuit provides a specific logic supply voltage with a level higher than the level of the main logic supply voltage. This specific voltage may in practice be chosen from the permissible range of values for circuits supplied with five volts, namely between 3 to 7 volts in practice. The remainder of the circuit is supplied by the main logic supply voltage (1 to 3 volts).
An approach of this kind makes it possible to continue using all the modes of access to the memory such as the page mode (or the total memory array write mode, etc.), these being modes that can be used to save a great deal of time. This is especially advantageous in terms of test modes and customer configuration modes. Accordingly, time is saved and the cells are better programmed, i.e. with a quantity of charge beneath the gate that is sufficient to reduce the sensitivity of the cells to leakage (loss of charge).
In a numerical example, for a prior art memory supplied exclusively with two volts, the total erasure of the memory would then have to be done byte by byte, and this operation takes 24,000 ms for a memory with a 64-kilobyte capacity. With this memory, supplied, however, according to the invention with a specific logic supply of five volts for the generation of the high voltage and a main logic supply of two volts for the remainder of the integrated circuit, it is possible to carry out a total erasure of the memory. This operation then takes only 3 ms. This simple numerical example clearly shows the full value of the invention.
Furthermore, using a logic supply voltage with a higher level for the internal high voltage generation circuitry has practically no effect on the total consumption of the circuit. Indeed, in a memory circuit, the element that consumes the greatest amount of current is the internal read circuitry and, in the invention, this circuitry remains supplied by the main logic supply. The high voltage generation circuit, for its part, consumes practically nothing since the logic supply voltage is used by it in practice only to switch over transistor gates. There is thus a definite advantage here as compared with prior art approaches which, to improve the programming performance characteristics of the circuits provided with low supply voltage, make internal use of bootstrap stages which consume a great deal of current.
In practice the use of an integrated circuit with a low logic supply voltage (lower than five volts) with a specific supply for the internal high voltage generation circuitry will depend on the number of pins available on the package and the application in view. Thus, in certain cases, the specific supply pad is provided on the integrated circuit chip but when the chip is assembled in a package, this specific pad is connected to the main logic supply pin. It is then possible to apply the specific supply level, only when the chip has not yet been assembled, by means of a probe card, namely during the wafer test. Indeed, it is not possible to apply the specific supply voltage (between 3 to 7 volts) to the main supply pin, for the xe2x80x9clow voltagexe2x80x9d technology, especially at the level of certain inputs which would not withstand such a level.
In other cases, the pad is connected to a specific pin of the package. It is then possible to apply the specific supply voltage, not only by means of the probe card on the chip, but also by means of the specific pin after the chip has been assembled. It is then possible to use the specific voltage not only for the wafer test, but also for the final testing of the integrated circuit in the package. In this case, it is even possible to use of this specific voltage in the application, namely in the phase of customer configuration for the programming of initialization data in the memory according to the customer""s specifications and in an application mode. If this specific supply level is not used in the application, the main logic supply voltage will be applied to this pin. In this case, it would be noted that the customer configuration will also be done under main logic supply voltage.
As characterized, the invention therefore relates to a memory integrated circuit comprising an internal circuit for the generation of a programming high voltage and comprising a first pad to receive a main logic supply voltage below five volts. According to the invention, the integrated circuit comprises a second specific supply pad to supply the high voltage generation circuit, enabling the application of a specific logic supply voltage with a voltage level greater than that of the main logic supply voltage.